000 01326nam a22003137a 4500
001 11872674
003 usth
005 20190418174715.0
008 991220s2000 paua b 100 0 eng
020 _a0803126158
082 0 0 _a621.382
_222
245 0 0 _aGate dielectric integrity :
_bmaterial, process, and tool qualification /
_cDinesh C. Gupta and George A. Brown, editors.
260 _aWest Conshocken, Pa. :
_bASTM,
_cc2000.
300 _axi, 169 p. :
_bill. ;
_c23 cm.
490 _aCollection of Advanced Material Science and Nanotechnology Books
504 _aIncludes bibliographical references.
650 0 _aSemiconductor wafers
_xReliability.
650 0 _aIntegrated circuits
_xWafer-scale integration
_xReliability.
650 0 _aGate array circuits
_xMaterials.
650 0 _aSilicon oxide films
_xTesting.
650 0 _aDielectrics
_xTesting.
700 1 _aGupta, D. C.
_q(Dinesh C.)
700 1 _aBrown, George A.,
_d1937-
711 2 _aConference on Gate Dielectric Integrity
_d(1999 :
_cSan Jose, Calif.)
906 _a7
_bcbc
_corignew
_d1
_eocip
_f19
_gy-gencatlg
911 _aNNPhuong
942 _2ddc
_cCK
955 _ato ASCD pc20 12-20-99; jf02 12-22-99; jf08 12-22-99 to SL; jf12 to Dewey 12-22-99; aa07 12-23-99; CIP ver. jf03 07-24-00; jf12 to BCCD 07-26-00; copy 2 added jf16 to BCCD 04-19-01
999 _c19998
_d19998